Resume For Design Engineer

Robert

E-Mail: [email protected]
Phone No: +1-2025xxxxx

Experience Summary

• I am working as a Senior Engineer Consultant in xxxxxx Communication Technologies and my parent company is xxxxxx Communication Technologies, having total experience of 2.4 years which includes 7 months project training.
• Specialized on SOC Validation and Verification, SOC Gate level simulation ,FPGA Design and Verification.
• I have worked on x86,V53A Processor IP, AHB, SD/SDIO/SDXC host Controller IP, SDIO-UART Bridge IP development, SPI master in my career.

Career Goals

• To seek a challenging and career oriented job, which enables me to update with the emerging latest Technology and provides scope for widening the spectrum of my knowledge.
• My career aspirations revolve around job satisfaction, responsibilities and to extent on the remuneration offered to me.
• Ambitious, positive attitude, hard working and fast on-the-job learning are my strengths.
• With my technical and communication skills, I am confident of handling any suitable assignment in projects and rise to the occasion and time.

Professional Qualification

• Master of Engineering in VLSI Systems (Year 2005 – 2007) From NITxxxx.

Academic profile

• B.E. (Electronics and Communication Engineering), XXXXXX University, 2003
• Percentage: 85.12%.

Skills Set

• Operating system: WINDOWS, Linux, Solaris
• HDLs: Verilog
• HVL: Open Vera
• Simulators: Model sim, Noves Verdi
• FPGA Tools: Xilinx ISE and Actel Libero
• FPGAs: Xilinx Spartan3E, Spartan3AN, Spartan6 and Actel ProASIC3
• Processors: Intel x86, NEC V53A and ARM7
• Programming Languages: Assembly, C, C++, Shell scripting and TCLBus
• Architectures: SDXC, SDIO, Wishbone, AHB, UART, SPI
• Memory Interfaces: DDR2 SDRAM
• Hardware tools: Tektronix Logic Analyzer and DSO
• Emulation tools: Quickturn palladium

Job Experience

From the beginning working with XXXX Communications from June 2009 till Date.

Project Details:

Project 1: SDXC Host Controller IP Verification

Description:

• Supports 32 bit AHB LITE synchronous Slave interface working at interface frequency.
• 1-bit/4-bit modes of SD/SDIO supported. Supports various clock frequencies such as 25MHz, 50MHz, 100MHz required for SD/ SDIO operations.
• Operating frequency configurable through registers. It is Compliant with SD specification version 3.0.

Organization: XXXXXXX Systems Technologies Pvt. Ltd.
Duration: 6 months
Team size: 2 members
Contribution: Test plan, Test Case, Simulation and Target testing
Domain: FPGA Verification
Technology Skills: Verilog

Project 2: Digital Image browser (iChart) Application

Description:

• The SPI controller’s primary function is to read configuration settings from the data flash after power on and also write the configuration settings into it.
• It consists of SPI master state machine and shifter logic.
• Read/write operation to and from the data flash can be accomplished by sending commands, address and data using the SPI controller.

Organization: XXXXX Systems Technologies Pvt. Ltd.
Duration: 8 months
Team size: 4 members
Contribution: SPI Controller and Application Control logic RTL design , Test plan , Simulation and testing
Domain: FPGA Design and Verification
Technology Skills: Verilog

Project 3: SDIO-UART Bridge IP Development

Description:

• Compliant with SD Physical Specification Version 2.00 and SDIO Specification Version 2.00.
• Here the Physical bus interface takes care the Command and Data bus interface. Supports SPI, 1-bit and 4bit SD modes and SDIO interrupts.
• This supports CRC checking and generation for both Command and Data. SDIO Function0 registers and other registers are supported as per the SDIO specification.
• A Wishbone interface is supported to interface Device Function Area and user function.

Organization: XXXXXX Systems Technologies Pvt. Ltd.
Duration: 9 months
Team size: 4 members
Contribution: SDIO Slave Controller RTL Design, Test plan ,Test Case, Simulation and Target testing
Domain: FPGA Design and Verification
Technology Skills: Verilog

Project 4: x86 Processor IP Development

Description:

• The Interrupt Controller can process external interrupt request, Internal Interrupt request inputs by allocating a priority level to the each request.
• It transfers the interrupt with highest priority to the CPU, along with interrupt address information.
• Interrupt routine address, interrupt request priority and masking are all under complete program control.
• Each Interrupt has a unique vector type.

Organization: XXXXXX Systems Technologies Pvt. Ltd.
Duration: 9 months +7 months project training
Team size: 5 members
Contribution: 80188EB, 80188EC & 80188XL Interrupt controller RTL Design, Test plan, Test Case, Simulation and Target testing
Domain: FPGA Design and Verification
Technology Skills: Verilog

Awards / Prizes

• Received “Project Quality Appreciation Award”, while working in XXXXX Systems Technologies Pvt. Ltd. College Second in Graduation.
• Third prize in paper presentation (National level) in XXXXXXXXX College of Technology.
• Won First place in Weight-lifting(University Level)

Extra Curricular Activities and Hobbies

• Listening to Music & GYM.
• Playing football.

Personal Profile

• Date of Birth: 12/6/1992
• Address: xxxxxxx